1. Field of the Invention
The present invention relates to a memory device and method of operating such a memory device, and in particular to techniques that can be employed when performing memory access operations to assist those memory access operations.
2. Description of the Prior Art
There is an increasing demand for memory devices to be constructed which are smaller and consume less power than their predecessor designs, whilst retaining high performance. New technologies are being developed which allow a reduction in size of the individual transistors making up each memory cell. However, as the memory cells decrease in size, the variation in behaviour between individual memory cells tends to increase, and this can adversely affect predictability of operation. This variation in operation of the individual memory cells can give rise to significant failure rates when trying to run the memory devices at high speed to meet the performance requirements. It is often also the case that there is a desire to use a lower power supply voltage for the memory device in order to reduce power consumption, but this can further increase the likelihood of failed operation within individual memory cells. Accordingly, in modern technologies, it is becoming more and more difficult to produce memory devices where the individual memory cells have the required stability to ensure effective retention of data (stability sometimes being measured in terms of static noise margin (SNM)), whilst also having required write-ability (WM) to ensure that new data values can be stored in the cells within the time period allowed for a write operation.
Faced with these issues, various assistance mechanisms have been developed which seek to assist individual memory cells in operating correctly when write and read operations are performed on those cells. For example, the article “A 3-GHz 70 Mb SRAM in 65 nm CMOS Technology with Integrated Column-Based Dynamic Power Supply” by K Zhang et al, Intel, published in ISSCC 2005, Session 26, describes a six transistor SRAM cell (often referred to as a 6T SRAM cell) which is stable in all conditions, but requires write assist (WA) circuitry to improve the likelihood of individual cells operating correctly when written to. The write assist circuitry disclosed in this article is illustrated schematically in FIG. 1, and is based on the idea of lowering the supply voltage to an addressed memory cell just prior to the write operation, the lower supply voltage lowering the stability of the memory cell, and therefore making it more easy to write into.
FIG. 1 shows an array of memory cells 240, 242, 244, 246, 248, 250, 252, 254 provided in association with a particular column multiplexer 260 of the memory array. Each row is addressed by a word line 200, 202, and each column has a power supply voltage provided by a supply voltage line 230, 232, 234, 236. As is known in the art, each of the columns also has a pair of bit lines 210, 212, 214, 216, 218, 220, 222, 224 associated therewith. From an address provided to the memory device, a row and column within the memory device is identified, with the addressed memory cell being the memory cell at the intersection between the identified row and column. For a read operation, the word line 200, 202 associated with the selected row is selected in order to enable a row of cells, and then the column multiplexer 260 outputs to the sense amplifier 270 an indication of the voltages on the pair of bit lines associated with the selected column to allow the sense amplifier to detect the value stored in the addressed memory cell. For a write operation, the word line is enabled in the same manner, and the voltage on one of the pair of bit lines associated with the selected column is then discharged to identify the data value to be stored in the addressed memory cell.
As shown in FIG. 1, associated with each supply voltage line, a multiplexer 262, 264, 266, 268 is provided which can select between a main supply voltage on path 275 and a specially generated lower column supply voltage provided over path 280. Just prior to the write operation, the relevant multiplexer 262, 264, 266, 268 associated with the selected column is driven to select, as the voltage output on the supply voltage line for that column, the reduced column supply voltage received over path 280. Hence, by way of example, if cell 240 is to be written to, then multiplexer 262 will output the lower column supply voltage received over path 280 to the supply voltage line 230. This will assist in performing the write operation with respect to the addressed memory cell 240. The other memory cells 248 in the selected column are not activated, since their associated word lines have not been enabled, and accordingly retain their held data values. For the other memory cells 242, 244, 246 coupled to the enabled word line 200, the supply voltage lines 232, 234, 236 are retained at the normal main supply voltage provided over path 275, since otherwise they could become unstable.
By such an approach, a higher yield can be produced, since memory cells that might otherwise fail the write-ability requirements can be caused to pass the required write-ability requirements by virtue of the reduced supply voltage used during the write operation. However, the implementation disclosed in FIG. 1 has a number of problems. Firstly, the time available to lower the supply voltage during the write operation is extremely limited, due to the short time available for performing write operations in high performance memory devices. The charge that needs to be dissipated when reducing the voltage on the supply line hence leads to large current peaks. Further, the memory requires for every output bit the use of a column with the supply voltage lowered, and this accordingly increases the current peak problem mentioned above.
Further, the design of FIG. 1 requires a dedicated voltage generator to produce the extra reduced column supply voltage over path 280, and this either needs to be accommodated within the design of the memory device, or else provided externally, with additional metal lines being provided to route the voltage supply from that voltage generator. For any change in height or width of the memory device, the capacitances observed on the various column supply voltage lines will change, and this will typically require a redesign or tuning of the voltage generator used to generate the extra column supply voltage on path 280, to ensure that the voltage on the column supply voltage line can be reduced sufficiently quickly in the short period of time allowed before the write occurs to the addressed memory cell. Such voltage generators will also be susceptible to temperature and voltage variations, which may require correcting circuits to be added.
In addition to these problems, in memory devices designed for low power applications, the presence of the additional voltage generator leads to significant power consumption since the additional voltage supply must be maintained at all times to enable that supply voltage to be available ahead of any write operation.
In the articles “An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage” by H Pilo et al, IEEE Journal of Solid-State Circuits, Volume 42, No. 4, April 2007, and “An SRAM Design in 65 nm and 45 nm Technology Nodes Featuring Read and Write-assist Circuits to Expand Operating Voltage” by H Pilo et al, 2006 Symposium on VLSI Circuits, Digest of Technical Papers, a write-assist feature is described which also makes use of an additional column supply voltage (referred to in the articles as VWR) for coupling to a column containing an addressed memory cell to be written to. In accordance with the technique described therein, a special onboard voltage generator is provided for globally generating the VWR voltage from the VDD supply voltage. This onboard voltage generator uses a push-pull transistor stage in order to generate the VWR voltage level. Band gap reference circuits are also used for the push-pull transistor stage. A disadvantage of such an approach is that a significant DC current is produced by the band gap generator circuitry used, and power is lost in charging and discharging the column supply line with different voltages every write cycle. Hence, such an approach is likely to be unacceptable in many memory devices, for example those designed for low power applications. Further, the band gap generator and push-pull transistor stage consume valuable space within the memory device.
The article “A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability with Read and Write Operation Stabilizing Circuits” by S Ohbayashi et al, IEEE Journal of Solid-State Circuits, Volume 42, No. 4, April 2007, describes a capacitive write assist circuit, where an additional metal line (referred to as the downvdd line in the article) is formed in a fourth metal layer, and preset to ground potential. During the write operation that downvdd line is connected to the relevant column supply voltage line in a second metal layer to cause charge redistribution to occur between the connected column supply voltage line and the downvdd line, leading to a drop in voltage on the column supply voltage line. Whilst this approach can reduce the voltage on the column supply voltage line very quickly, it does require the provision of an extra metal line within the memory circuit, along with the use of a pre-charge circuit in association with that extra line to precharge that line to a ground level, giving rise to power loss associated with such precharge circuits. The provision of such an additional line is likely to increase cost, and may prove difficult to incorporate within high density memory designs. Further, the increase in power consumption associated with the precharge circuits provided for that additional line may be unacceptable in certain memory devices, for example those designed for low power applications.
The article “A 45 nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations” by M Yabuuchi et al, published in ISSCC 2007, Session 18, describes a similar write assist circuit making use of an additional line to share charge with the selected column supply voltage line during a write operation.
The article “A New Single-Ended SRAM Cell with Write-Assist” by R Hobson, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 15, No. 2, February 2007, describes a 6T SRAM cell with a write-assist feature. A single-ended I/O (SEIO) bit line variation on the 6T SRAM structure is proposed where both reading and writing take place over a common SEIO bit line, and a floating ground line is used in place of the traditional second bit line. During a write operation, the floating ground line is selectively connected to one of the internal nodes of the memory cell to improve write-one performance. The disadvantages of such an approach are that it involves a significant modification to the standard SRAM memory cell, results in a non-regular layout which may prove difficult to implement, and will result in a slow read operation due to the use of a single bit line.
Accordingly, it would be desirable to provide an improved form of assist mechanism for use in a memory device, which is simpler, and consumes less power, than the known prior art techniques.